Reconfigurable systolic arrays can be adapted to efficiently resolve a wide 
spectrum of computational problems; parallelism is naturally explored in 
systolic arrays and reconfigurability allows for redefinition of the 
interconnections and operations even during run time (dynamically). We present a 
reconfigurable systolic architecture that can be applied for the efficient 
treatment of several dynamic programming methods for resolving well-known 
problems, such as global and local sequence alignment, approximate string 
matching and longest common subsequence. The dynamicity of the reconfigurability 
was found to be useful for practical applications in the construction of 
sequence alignments. A VHDL (VHSIC hardware description language) version of 
this new architecture was implemented on an APEX FPGA (Field programmable gate 
array). It would be several magnitudes faster than the software algorithm 
alternatives.